Core Configuration
OMR[MA–MD] bits), and the reset vector address to which the DSP56311 jumps once it leaves
the Reset state.
Table 4-1. DSP56311 Operating Modes
Mode
0
MODD
0
MODC
0
MODB
0
MODA
0
Reset
Vector
$C00000
Expanded mode
Description
Bypasses the bootstrap ROM, and the DSP56311
starts fetching instructions beginning at address
$C00000. Memory accesses are performed using
SRAM memory access type with 31 wait states and
no address attributes selected (default). Address
$C00000 is reflected as address $00000 on Port A
signals A[0–17].
1
2
3
4
5
6
7
8
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
$FF0000
$FF0000
$FF0000
$FF0000
$FF0000
$FF0000
$FF0000
$008000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Expanded mode
Bypasses the bootstrap ROM, and the DSP56311
starts fetching instructions beginning at address
$008000. Memory accesses are performed using
SRAM memory access type with 31 wait states and
no address attributes selected.
9
1
0
0
1
$FF0000
Bootstrap from byte-wide memory
The bootstrap program loads instructions through
Port A from external byte-wide memory, starting at
P:$D00000. The SRAM memory access type is
selected by the values in address attribute register 1
(AAR1). Thirty-one wait states are inserted between
each memory access. Address $D00000 is reflected
as address $00000 on Port A signals A[0–17]. The
boot program concatenates every 3 bytes read from
the external memory into a 24-bit wide DSP56311
word.
DSP56311 User’s Manual, Rev. 2
4-2
Freescale Semiconductor
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